1. Field of the Invention
The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly, it relates to a semiconductor device having a gate electrode and a method of fabricating the same.
2. Description of the Prior Art
A salicide (self-aligned silicide) process is generally known as a process for reducing the resistance of a gate electrode and source/drain regions of a MOS transistor. In this salicide process, a low-resistance metal silicide film is formed on the gate electrode and the source/drain regions in a self-aligned manner.
When employing the aforementioned salicide process in a step of forming a MOS transistor, extremely high-grade technique is required for setting conditions in this step. If a heat treatment (annealing) temperature is excessive, for example, silicide films grow also on side wall spacers, to disadvantageously result in defective short-circuiting (bridging) across the gate electrode and the source/drain regions.
FIG. 18 is a sectional view of a conventional semiconductor device for illustrating defective bridging. Defective bridging in the conventional semiconductor device is now described in detail with reference to FIG. 18. In the conventional semiconductor device, field oxide films 102 are formed on element isolation regions of a silicon substrate 101. A pair of source/drain regions 109 are formed on an element forming region enclosed with the field oxide films 102, to hold a channel region therebetween. A gate electrode 104 consisting of a polycrystalline silicon film is formed on the channel region through a gate insulator film 103. Side wall spacers 108 are formed on both side walls of the gate electrode 104.
In order to apply the salicide process to the conventional semiconductor device having the aforementioned structure, a Ti film 105 is first formed on the overall surface. Thereafter heat treatment is performed for simultaneously forming metal silicide films 106 on the upper surface of the gate electrode 104 and the surfaces of the source/drain regions 109. If the heat treatment (annealing) temperature is excessive in this case, metal silicide films 106a abnormally grow on the side wall spacers 108, to disadvantageously short-circuit the gate electrode 104 and the source/drain regions 109.
When the heat treatment (annealing) temperature is too small contrarily to the above, the silicide films 106 so insufficiently grow that the resistance cannot be sufficiently reduced by the salicide process.
Thus, the range of the conditions for setting the heat treatment is narrow in the conventional salicide process, to disadvantageously result in small process tolerance (process margin).
In order to cope with such an inconvenience that the resistance cannot be sufficiently reduced by the salicide process, Japanese Patent Laying-Open No. 10-65171 (1998) proposes a method of supplying a sufficient silicide film to a gate electrode. According to this proposed technique, the gate electrode is formed by two layers of a polysilicon layer and a first Ti silicide layer while a second Ti silicide layer is formed on the gate electrode and source/drain regions. Thus, the first and second TI silicide layers define a thick silicide layer for the gate, so that the gate electrode can be formed with a sufficient silicide film as compared with the general salicide process.
Also in the aforementioned proposed technique, however, defective bridging may be caused across the gate electrode and the source/drain regions when forming the second Ti silicide layer, and it is difficult to solve the problem of such defective bridging. In general, therefore, defective short-circuiting (defective bridging) must regularly be taken into consideration and hence the process margin (process tolerance) is disadvantageously reduced.
When forming contact holes 113a and 113b in an interlayer isolation film 113 covering the overall surface by etching upon employment of the salicide process as shown in FIG. 19, the etching may not be stopped in the metal silicide film 106 formed on the gate electrode 104 due to the difference between the thicknesses of portions of the interlayer isolation film 113 located on the source/drain regions 109 and the gate electrode 104.
In this case, the contact hole 113b passes through the metal silicide film 106 to reach the gate electrode 104, and further reaches the gate insulator film 103 at the worst. In this case, the gate insulator film 103 is damaged to deteriorate the characteristics of the gate electrode 104. When the contact hole 113b passes through the metal silicide film 106 to reach the gate electrode 104, it follows that an upper-layer wire comes into contact only with the side surfaces of the metal silicide film 106 and hence the contact area between the upper-layer wire and the metal silicide film 106 is reduced. Thus, contact characteristics are also disadvantageously deteriorated.
An object of the present invention is to provide a semiconductor device capable of effectively preventing a gate electrode and impurity regions from defective short-circuiting and reducing the resistance of the gate electrode and the impurity regions.
Another object of the present invention is to prevent a contact hole formed on the gate electrode from punch-through in the aforementioned semiconductor device.
Still another object of the present invention is to provide a method of fabricating a semiconductor device capable of readily forming a low-resistance compound layer by increasing process tolerance.
A semiconductor device according to an aspect of the present invention comprises a pair of impurity regions, a first gate film, a second gate film, a second compound layer and a reaction preventing film. The pair of impurity regions are formed on the main surface of a semiconductor substrate at a prescribed interval to hold a channel region therebetween. The first gate film is formed on the channel region through a gate insulator film. The second gate film is formed on the first gate film, and consists of a first compound layer. The second compound layer is formed on the surfaces of the impurity regions. The reaction preventing film is formed on the second gate film for preventing reaction between the first compound layer and the second compound layer. In the present invention, the term xe2x80x9csemiconductor substratexe2x80x9d indicates a wide concept including not only a general semiconductor substrate but also a semiconductor thin film or the like.
In the semiconductor device according to the aforementioned aspect, the reaction preventing film for preventing reaction between the first compound layer and the second compound layer is so provided that the first compound layer and the second compound layer are formed independently of each other without reaction, whereby the first compound layer and the second compound layer are prevented from connection. Thus, the gate electrode and the impurity regions can be effectively prevented from defective short-circuiting. The first compound layer and the second compound layer are formed independently of each other without reaction, whereby process tolerance is increased. Thus, the first and second compound layers can be readily formed in lower resistance as compared with the prior art, for consequently reducing the resistance of the gate electrode and the impurity regions. Thus, the speed of the semiconductor device can be increased.
In the semiconductor device according to the aforementioned aspect, the reaction preventing film preferably includes a conductive film consisting of a material selected from a group consisting of a low-resistance metal, a high melting point metal and a high melting point metal compound. When formed by such a conductive film, the reaction preventing film serves as parallel resistance of the gate electrode, whereby the resistance of the gate electrode can be further reduced. Consequently, the speed of the semiconductor device can be further increased.
Preferably, the semiconductor device according to the aforementioned aspect further comprises an interlayer isolation film formed to cover the second gate film and the second compound layer, and the reaction preventing film contains a material having a high etching selection ratio with respect to the interlayer isolation film. When prepared from a material having a high selection ratio with respect to the material for the interlayer isolation film such as a silicon oxide film in the aforementioned manner, the reaction preventing film can be employed as an etching stopper film when forming a contact hole in the interlayer isolation film by etching. Thus, the contact hole can be effectively prevented from passing through the first compound layer and reaching the first gate film. Consequently, it is possible to prevent deterioration of the gate electrode characteristics resulting from damage of the gate insulator film caused when the contact hole reaches the gate insulator film or deterioration of contact characteristics resulting from reduction of a contact area between the first compound layer and an upper layer wire. In this case, the reaction preventing film preferably includes a film consisting of a material selected from a group consisting of a nitrogen compound, an oxide other than an Si oxide, a high melting point metal and a high melting point metal compound. The reaction preventing film having a high etching selection ratio with respect to the interlayer isolation film consisting of a silicon oxide film or the like can be readily formed by employing the aforementioned material.
In the semiconductor device according to the aforementioned aspect, the reaction preventing film preferably includes a film consisting of a material selected from a group consisting of a high melting point Si compound, a high melting point metal and a high melting point metal compound. When prepared from such a material having high chemical resistance and high heat resistance, the reaction preventing film can prevent the gate electrode from exposure to a high-temperature mixed solution of ammonia and hydrogen peroxide or the like employed for treatment in a washing step carried out before forming the interlayer isolation film, for example. Further, the reaction preventing film having high heat resistance can effectively prevent the first compound layer, located under the reaction preventing film, from deformation caused by heat.
A semiconductor device according to another aspect of the present invention comprises a pair of impurity regions, a gate electrode consisting of a single layer, a first compound layer, a second compound layer and a side wall insulator film consisting of a single layer. The pair of impurity regions are formed on the main surface of a semiconductor substrate at a prescribed interval to hold a channel region therebetween. The gate electrode is formed on the channel region through a gate insulator film. The first compound layer is formed on the gate electrode. The second compound layer is formed on the surfaces of the impurity regions. The side wall insulator film is formed on the side surface of the gate electrode, and has a first concave portion on its surface.
In the semiconductor device according to the aforementioned aspect, the side wall insulator film consisting of a single layer having the first concave portion is provided on the side surface of the gate electrode consisting of a single layer for separating a conductor film for forming the first compound layer and the second compound layer in a self-aligned manner with the first concave portion in the process of formation. Thus, a solid phase diffusion path between the first compound layer and the second compound layer is cut off in formation of the first and second compound layers, whereby the first and second compound layers can be prevented from connection. Consequently, the gate electrode and the impurity regions can be effectively prevented from defective short-circuiting. The solid phase diffusion path between the first and second compound layers is cut off in formation of the first and second compound layers, whereby process tolerance is increased. Thus, the first and second compound layers can be readily formed in lower resistance as compared with the prior art, thereby further reducing the resistance of the gate electrode and the impurity regions as a result. Consequently, the speed of the semiconductor device can be increased. Further, the aforementioned effect ca be attained with a simple structure by providing the side wall insulator film of a single layer having the first concave portion on the side surface of the gate electrode consisting of a single layer.
In the semiconductor device according to the aforementioned aspect, the first concave portion is preferably formed to be depressed sideward from the surface of the side wall insulator film. When the first concave portion is formed in such a manner, a conductor film for forming the first compound layer and the second compound layer can be readily separated with the first concave portion.
In the semiconductor device according to the aforementioned aspect, the side wall insulator film preferably includes an arcuate surface, and an insulator film consisting of a material different in etching rate from the side wall insulator film is preferably formed on the arcuate surface of the side wall insulator film. Thus, the surface of the side wall insulator film can be partially depressed by etching the side wall insulator film through the insulator film serving as a mask, whereby the first concave portion can be readily formed.
In the semiconductor device according to the aforementioned aspect, the side wall insulator film preferably includes a second concave portion formed on an upper portion of the boundary region between the side wall insulator film and the gate electrode, and the first concave portion is preferably formed at a prescribed interval from the second concave portion. When the second concave portion is formed on the upper portion of the boundary region between the side wall insulator film and the gate electrode in the aforementioned manner, an upper portion of the side surface of the gate electrode is exposed. Thus, the first compound layer formed by reaction with the gate electrode is formed also on the side surface of the gate electrode, whereby the resistance of the gate electrode can be further reduced.
A method of fabricating a semiconductor device according to still another aspect of the present invention comprises steps of forming a first conductor film on a channel region provided on the main surface of a semiconductor substrate through a gate insulator film, forming a second conductor film on the first conductor film, forming a reaction preventing film on the second conductor film, performing first treatment on the first conductor film and the second conductor film thereby reacting the first conductor film and the second conductor film with each other for forming a first compound layer, forming a pair of impurity regions at a prescribed interval to hold the channel region therebetween, forming a third conductor film to cover the reaction preventing film and the impurity regions, and performing second treatment thereby reacting the third conductor film and a semiconductor forming the impurity regions for forming a second compound layer while preventing the first compound layer and the second compound layer from reacting with each other by the reaction preventing film during the second treatment. In the present invention, the term xe2x80x9csemiconductor substratexe2x80x9d indicates a wide concept including not only a general semiconductor substrate but also a semiconductor thin film or the like.
In the method of fabricating a semiconductor device according the aforementioned aspect, the reaction preventing film prevents the first and second compound layers from reacting with each other during the second treatment, whereby the first and second compound layers are formed independently of each other without reaction and prevented from connection. Thus, the gate electrode and the impurity regions can be readily prevented from defective short-circuiting. The first and second compound layers are formed independently of each other without reaction in formation of the second compound layer, whereby process tolerance is increased. Thus, the first and second compound layers can be readily formed in lower resistance as compared with the prior art.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the reaction preventing film preferably includes a conductive film consisting of a material selected from a group consisting of a low-resistance metal, a high melting point metal and a high melting point metal compound. When formed by such a conductive film, the reaction preventing film serves as parallel resistance of the gate electrode, whereby the resistance of the gate electrode can be further reduced. Consequently, the speed of the semiconductor device can be further increased.
The method of fabricating a semiconductor device according to the aforementioned aspect preferably further comprises a step of forming an interlayer isolation film to cover the second gate film and the second compound layer, and the reaction preventing film preferably contains a material having a high etching selection ratio with respect to the interlayer isolation film. When prepared from a material having a high selection ratio with respect to the material for the interlayer isolation film such as a silicon oxide film in the aforementioned manner, the reaction preventing film can be employed as an etching stopper film when forming a contact hole in the interlayer isolation film by etching. Thus, the contact hole can be effectively prevented from passing through the first compound layer and reaching the first gate film. Consequently, it is possible to prevent deterioration of the gate electrode characteristics resulting from damage of the gate insulator film caused when the contact hole reaches the gate insulator film or deterioration of contact characteristics resulting from reduction of a contact area between the first compound layer and an upper layer wire. In this case, the reaction preventing film preferably includes a film consisting of a material selected from a group consisting of a nitrogen compound, an oxide other than an Si oxide, a high melting point metal and a high melting point metal compound. The reaction preventing film having a high etching selection ratio with respect to the interlayer isolation film consisting of a silicon oxide film or the like can be readily formed by employing the aforementioned material.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the reaction preventing film preferably includes a film consisting of a material selected from a group consisting of a high melting point Si compound, a high melting point metal and a high melting point metal compound. When prepared from such a material having high chemical resistance and high heat resistance, the reaction preventing film can prevent the gate electrode from exposure to a high-temperature mixed solution of ammonia and hydrogen peroxide or the like employed for treatment in a washing step carried out before forming the interlayer isolation film, for example. Further, the reaction preventing film having high heat resistance can effectively prevent the first compound layer, located under the reaction preventing film, from deformation caused by heat.
Preferably, the first treatment includes first heat treatment, the second treatment includes second heat treatment, and the first heat treatment and the second heat treatment are simultaneously performed. Thus, the fabrication process can be simplified as compared with the case of performing the first heat treatment and the second heat treatment independently of each other.
A method of fabricating a semiconductor device according to a further aspect of the present invention comprises steps of forming a first conductor film consisting of a single layer on a channel region provided on the main surface of a semiconductor substrate through a gate insulator film, forming a side wall insulator film consisting of a single layer having a first concave portion on the side surface of the first conductor film, forming a pair of impurity regions at a prescribed interval to hold the channel region therebetween, forming a second conductor film by sputtering to cover the first conductor film and the impurity regions, and performing treatment on the first conductor film, the impurity regions and the second conductor film thereby reacting the first conductor film and the second conductor film with each other for forming a first compound layer while reacting the second conductor film and a semiconductor forming the impurity regions with each other for forming a second compound layer.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the second conductor film for forming the first compound layer and the second compound layer is formed by sputtering after forming the side wall insulator film having the first concave portion, so that the second conductor film is separated in a self-aligned manner with the first concave portion in the process of formation. Thus, a solid phase diffusion path between the first compound layer and the second compound layer is cut off in formation of the first and second compound layers, whereby the first and second compound layers can be prevented from connection. Consequently, a gate electrode (first conductor film) and the impurity regions can be effectively prevented from defective short-circuiting. Further, process tolerance is increased since the solid phase diffusion path between the first and second compound layers is cut off in formation thereof. Thus, the first and second compound layers can be readily formed in lower resistance as compared with the prior art, so that the resistance of the gate electrode and the impurity regions can be further reduced as a result. Thus, the speed of the semiconductor device can be increased. Further, the side wall insulator film of a single layer having the first concave portion is provided on the side surface of the first conductor film (gate electrode) of a single layer, whereby the aforementioned effect can be attained through a simpler process as compared with the case of employing a plurality of layers.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the step of forming the side wall insulator film having the first concave portion preferably includes steps of forming an insulator film consisting of a material different in etching rate from the side wall insulator film to cover the side wall insulator film and thereafter etching back the insulator film so that the insulator film remains only on a prescribed portion of the surface of the side wall insulator film, and isotropically etching the side wall insulator film through the remaining insulator film serving as a mask thereby forming the first concave portion. When isotropically etching the side wall insulator film through the insulator film remaining only on the prescribed portion of the surface of the side wall insulator film, the first concave portion can be readily formed.
In this case, the method of fabricating a semiconductor device preferably further comprises a step of isotropically etching the side wall insulator film through the remaining insulator film serving as a mask thereby simultaneously forming a second concave portion on an upper portion of the boundary region between the side wall insulator film and the gate electrode in addition to the first concave portion. When the second concave portion is formed on the upper portion of the boundary region between the side wall insulator film and the gate electrode in the aforementioned manner, an upper portion of the side surface of the gate electrode is exposed. Thus, the first compound layer formed by reaction with the gate electrode is also formed on the side surface of the gate electrode, whereby the resistance of the gate electrode can be further reduced. Further, the second concave portion is formed simultaneously with the first concave portion, not to complicate the fabrication process by newly providing the second concave portion.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the step of forming the side wall insulator film having the first concave portion preferably includes steps of forming a resist film exposing a prescribed portion of the side wall insulator film and forming the first concave portion by isotropically etching the side wall insulator film through the resist film serving as a mask. When employing the resist film and isotropic etching in the aforementioned manner, the first concave portion can be readily formed to be depressed sideward from the surface of the side wall insulator film.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the first concave portion is preferably formed to be depressed sideward from the surface of the side wall insulator film. When forming the first concave portion in the aforementioned manner, a conductor film for forming the first and second compound layers can be readily separated with the first concave portion in the process of formation.
In the method of fabricating a semiconductor device according to the aforementioned aspect, the side wall insulator film preferably includes an arcuate surface, and an insulator film consisting of a material different in etching rate from the side wall insulator film is preferably formed on the arcuate surface of the side wall insulator film. Thus, the surface of the side wall insulator film can be partially depressed by etching the side wall insulator film through the insulator film serving as a mask, so that the first concave portion can be readily formed as a result.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.